FIG. 4 is a sectional view showing the structure of a typical conventional TFT 1 for use in the active matrix type liquid crystal display device. The TFT 1 is provided with a substrate 2, which is made of resin or glass and is an electrical insulating material. There are laminated on the substrate 2 a gate electrode 3 which has a stripe shape and is made of a metallic thin film such as chrome, a gate insulating layer 4 made of SiNx, a semiconductor layer 5 made of amorphous silicon, a channel protective layer 11, ohmic contact layers 6 and 7 in which an impurity such as phosphorus are doped, a source electrode 8 and a drain electrode 9 which are respectively made of a metal such as chrome, and a protective layer 10 in this order. The TFT 1 wherein the gate electrode 3 is first provided on the substrate 2 in the foregoing manner is called as a reverse staggered type TFT.
According to the TFT 1, in the case where the ohmic contact layers 6 and 7 are provided on the semiconductor layer 5, the channel protective layer 11 is provided on the semiconductor layer 5 so that the semiconductor layer 5 is not etched when etching a channel part 12. By the channel part 12 the ohmic contact layer 6 is separated from the ohmic contact layer 7 in accordance with the source electrode 8 and the drain electrode 9 respectively, the respective ohmic contact layers 6 and 7 being uniformly laminated on the semiconductor layer 5.
According to the TFT 1 having the channel protective layer 11, its element becomes greater in size. When the TFT 1 is used in the liquid crystal display device, there arises the problem that an aperture ratio of each element becomes small since each pixel becomes greater in size. To solve the problem, it is well known that a TFT 21 without the channel protective layer 11 can be used (see FIG. 5). The same reference numerals are assigned to the members and means of FIG. 5 which are analogous to or correspond to those of FIG. 4.
A process for manufacturing a plurality of the TFTs 21 on the substrate 2 is explained below referring to FIGS. 6 and 7. First, a metal such as Al, Mo, or Ta etc. is laminated by the sputtering method on the substrate 2, and a gate electrode 3 is formed by patterning the sputtered metal (see step s1). Next, the gate insulating layer 4 is laminated on the gate electrode 3 by the plasma CVD method (see step s2). Then, the semiconductor layer 5, and the ohmic contact layers 6 and 7 are formed.(see step s3).
The semiconductor layer 5 is an i-type semiconductor and the respective ohmic contact layers 6 and 7 are n-type semiconductors. More specifically, the semiconductor layer 5, and the ohmic contact layers 6 and 7 are formed as follows. First the semiconductor layer 5 and the ohmic contact layers 6 and 7 are laminated in this order by the plasma CVD method on the gate insulating layer 4 (see steps s31 and s32). Next, a photoresist 23 is laminated on the ohmic contact layers 6 and 7 (see FIG. 6(a) and step s33). Then the photoresist 23 is patterned so that a channel formation region of each TFT 21 on the substrate 2 is covered (see step s34). Thereafter, the semiconductor layer 5, and the ohmic contact layers 6 and 7 are etched in accordance with the photoresist 23 (see FIG. 6(b) and step s35). Then, the photoresist 23 is removed in step s36, thereby completing the process of a channel formation.
The source electrode 8 and the drain electrode 9 are formed so that the electrodes 8 and 9 are laminated by the sputtering method, and thereafter are patterned (see FIG. 6 (c) and steps s4 and s5). Thereafter, the channel part 12 is etched to separate the ohmic contact layer 6 from the ohmic contact layer 7 (see steps s6).
The etching of the channel part 12 is carried out in the following manner. First, a photoresist 24 is laminated as shown in FIG. 6(d) and step s61, then the patterning is carried out in accordance with the channel part 12 (see step s62) and the etching process is further carried out with respect thereto (see FIG. 6(e) and step s63). After the separation of the ohmic contact layers 6 and 7, the photoresist 24 is removed in step s64. Then, the protective layer 10 is formed in step s7, thereby obtaining the TFT 21.
However, the TFT 21 and manufacturing method thereof present the following problems.
When the ohmic contact layers 6 and 7 and the semiconductor layer 5 are made of the same material such as amoruphous silicon, there is no choice to make a difference in the etching speeds between the ohmic contact layers 6 and 7, and the semiconductor layer 5. Accordingly, the depth of etching should be precisely controlled so that the semiconductor layer S is not etched during the etching with respect to the channel part 12 of the ohmic contact layers 6 and 7.
In the case where there is a difference in the etching speeds within the substrate 2, there exists a TPT 21 in which the semiconductor layer 5 is undesirably etched. For example, when the etching speed is faster in the periphery of the substrate 2 than that around the center, there presents the problem that the undesirable etching is carried out with respect to the semiconductor layer 5 of the TFT 21 in the periphery of the substrate 2 when the thorough etching is carried out with respect to the channel part 12 of the ohmic contact layers 6 and 7 of the TFT 21 around the center of the substrate 2. With the arrangement, (1) the number of defective products is greatly increased or (2) the thickness of the semiconductor layer 5 becomes thicker than is required, thereby causing that the TFT characteristic is more likely to be affected by the projected light.
Further, according to the conventional manufacturing process of the TFT 21, there presents, unlike the foregoing conventional manufacturing process of the TFT 1, the problem that the etching process for the channel formation and the etching process for the separation of the ohmic contact layers 6 and 7 can not be carried out in a single step. More specifically, (1) the etching process for the semiconductor layer 5 and the ohmic contact layers 6 and 7 (see FIG. 6(b) and step s35) and (2) the etching process for the channel part 12 (see FIG. 6(e) and step s63) can not be carried out in a same single process. This is based on the fact that the semiconductor layer 5 should also be etched in the etching process (1) while the semiconductor layer 5 should not be etched in the etching process (2).
On the other hand, Laid-open Japanese Patent Application No. 2-268468 discloses another conventional TFT manufacturing method wherein no such channel protective layer 11 is provided. According to the conventional TFT manufacturing method, the semiconductor layer 5 is made of amorphous silicon and the ohmic contact layers 6 and 7 are made of microcrystalline silicon. The microcrystalline silicon is composed of the crystal grains of several hundreds of .ANG. in size and have countless grain boundaries. In contrast, the amorphous silicon has no grain boundary because of its disordered structure. Therefore, in wet etching process, the penetration of the etchant into the grain boundaries (i,e., the etching rate) is faster in the microcrystalline silicon than in the amorphous silicon. Thus, such a difference in the respective etching rates is utilized to improve the etching accuracy of the channel part 12.
Since the dry etching process is carried out based on the gas phase reaction, the etching rate is not greatly affected by the crystalline structure provided that the element of the target to be etched is same. Thus, the conventional TFT manufacturing method presents the problem that the dry etching process can not be adopted. Further, the ohmic contact layers 6 and 7 should be made of the microcrystalline silicon and it takes much longer (e.g., double of the amorphous silicon) to grow the layer of the microcrystalline silicon than to grow the layer of the amorphous silicon. This causes the time for completing the step to be prolonged.